1. Field
The embodiments discussed herein are relates to a counter circuit provided in a dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of the reconfigurable processing elements and a connection content between the reconfigurable processing elements. The embodiments discussed herein also are related to the dynamic reconfigurable circuit and a loop processing control method used therein.
2. Description of the Related Art
Conventionally, the dynamic reconfigurable circuit is characterized by its capability of changing instructions from a computing unit and the connection between the computing units inside the circuit during an operation. Specifically, the dynamic reconfigurable circuit includes a plurality of reconfigurable processing elements (hereinafter, referred to as PEs). Configuration contents of the dynamic reconfigurable circuit are described as information, referred to as contexts, that indicates setting of an operation of each PE, and that of connections between the PEs. When the circuit is reconfigured, the computing processing contents or connections between PEs are changed in accordance with the contexts.
In the dynamic reconfigurable circuit, in accordance with the above-described contexts, processing contents or connection destinations of the PEs included in the circuit are sequentially changed. That is, even when different processings are performed, by performing the processings by dividing in a time axis direction, the PEs can be shared among the different processings. This brings about an advantage of allowing a reduction in the size of hardware in the overall dynamic reconfigurable circuit. Generally, in such dynamic reconfigurable circuit based on the contexts, a counter circuit is used for controlling the start and stop of the execution of each context. Specifically, a data-driven-reconfigurable counter is employed (for example, refer to Japanese Unexamined Patent Application Publication No. 2003-518666).
However, the conventional data-driven-reconfigurable counter only has a specialized function for application mounted in the dynamic reconfigurable circuit. Accordingly, if the counter circuit is mounted using a high-level language such as C language, it is difficult to perform count processing corresponding to so-called loop processing such as a “for” sentence or a “while” sentence.
Specifically, when a loop processing in the C language, which is a high-level language, is applied to the dynamic reconfigurable circuit, the configuration of the counter circuit must be changed to a configuration capable of counting any multiple loops described in the C language. However, because a maximum number of the multiple loops is determined according to specifications of the counter, each parameter in the loop processing must be changed in accordance with the specifications. Thus, the conventional dynamic reconfigurable circuit may not implement the loop processing described in the high-level language such as the C language. This causes a problem that implementable processings in the dynamic reconfigurable circuit will be undesirably limited.
Furthermore, in the conventional data-driven counter circuit, a counting operation is starts or controlled with a valid data inputted from the outside of the dynamic reconfigurable circuit as a trigger. Accordingly, when attempting to generate data to be an input to a PE in the dynamic reconfigurable circuit, a trigger signal indicating a start timing of the counter circuit cannot be generated.
Specifically, in the context switching in the dynamic reconfigurable circuit, in order to indicate a start timing of the counter circuit, it is preferable to use a control signal indicating termination timing of processing by a context currently being executed. However, in the case of an address count processing in the data-driven counter circuit, since a valid data input from the outside is used as a start trigger, it is not possible to use the internally generated control signal as a start indication of the counter circuit.
Also, in the case where, at a point of time when a particular loop processing having been ended, another loop processing is to be started, it is preferable to use an identical trigger signal for the start of a pre-stage counter circuit and the stop of a post-stage counter circuit. However, in the case of the data-driven counter circuit, since it is also impossible to determine the end of the pre-stage counter based on the valid data read from the pre-stage counter, another control must be added, which results in an increase in the number of PEs to be used.
In this manner, in the conventional counter circuit, it is not possible to output a signal corresponding to loop processing to be implemented at optional timing. In the dynamic reconfigurable circuit, therefore, when loop processing based on a description in a high-level language is implemented, extra PEs for the control is needed, which raises a problem of increasing the size of the hardware.